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1 ? x9420 low noise/low power/spi bus single digitally c ontrolled (xdcp?) potentiometer features ? solid-state potentiometer ? spi serial interface ? register oriented format ?direct read/write/tra nsfer wiper positions ?store as many as four positions per potentiometer ? power supplies ?v cc = 2.7v to 5.5v ?v+ = 2.7v to 5.5v ?v? = -2.7v to -5.5v ? low power cmos ?standby current < 1a ? high reliability ?endurance?100,000 data changes per bit per register ?register data retention?100 years ? 8-bytes of nonvol atile eeprom memory ?10k ? or 2.5k ? resistor arrays ? resolution: 64 taps each pot ? 14-lead tssop, 16-lead soic, and 16-pin plastic dip packages description the x9420 integrates a single digitally controlled potentiometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiomete r has associated with it a volatile wiper counter register (wcr) and 4 nonvolatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power-up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram r0 r1 r2 r3 wiper counter register (wcr) interface and control circuitry hold cs si a0 v h /r h v l /r l data 8 v w /r w sck s0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn8195.0 march 7, 2005
2 fn8195.0 march 7, 2005 pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9420. chip select (cs ) when cs is high, the x9420 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9420, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sc k is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 ) the address inputs is used to set the least significant bit of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9420. a maximum of 2 devices may occupy the spi serial bus. potentiometer pins v h /r h , v l /r l the v h /r h and v l /r l input are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w the wiper output is equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. writ ing to the wiper counter register is not restricted. analog supplies (v+, v-) the analog supplies v+, v- are the supply voltages for the xdcp analog section. system/digital supply (v cc ) v cc is the supply voltag e for the system/digital section. v ss is the system ground. pin configuration v cc cs r l /v l si wp v ss 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v+ nc a0 so hold sck nc v- dip/soic x9420 r h /v h r w /v w tssop v cc cs r l /v l si wp v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v+ a0 so hold sck v- x9420 r h /v h r w /v w x9420
3 fn8195.0 march 7, 2005 pin names principles of operation the x9420 is a highly integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the xdcp potentiometer. serial interface the x9420 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9420 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of the array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within the individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the block diagram of the potentiometer is shown in figure 1. wiper counter register (wcr) the x9420 contains a wiper counter register. the wcr can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instructio n (serial load); it may be written indirectly by transfer ring the contents of one of four associated data r egisters via the xfr data register instruction (paralle l load); it can be modified one step at a time by the increment/ decrement instruction. finally, it is lo aded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9420 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers the potentiometer has four 6-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiomete r, the data registers can be used as regular memory locations for system parameters or user preference data. register descriptions table 1. data registers, (6-bit), nonvolatile there are four 6-bit data registers associated with the potentiometer. ? {d5~d0}: these bits are for general purpose non- volatile data storage or for storage of up to four dif- ferent wiper values. table 2. wiper counter register, (6-bit), volatile ? {wp5~wp0}: these bits specify the wiper position of the potentiometer. symbol description sck serial clock si, so serial data a0 device address v h /r h , v l /r l potentiometer pins (terminal equivalent) v w /r w potentiometer pins (wiper equivalent) wp hardware write protection hold serial communication pause v+,v- analog supplies v cc system supply voltage v ss system ground nc no connection 0 0 d5 d4 d3 d2 d1 d0 (msb) (lsb) 0 0 wp5 wp4 wp3 wp2 wp1 wp0 (msb) (lsb) x9420
4 fn8195.0 march 7, 2005 figure 1. detailed potentiometer block diagram write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete wr ite sequence is received by the device. the progress of th is internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions address/identification (id) byte the first byte sent to the x9420 from the host, following a cs going high to low, is called the address or identification byte. the most significant four bits of the slave address are a device type identifier, for the x9420 this is fixed as 0101[b] (refer to figure 2). the least significant bit in the id byte selects one of two devices on the bus. the physical device address is defined by the state of the a 0 input pin. the x9420 compares the serial data stream with the address input state; a succ essful compare of the address bit is required for the x9420 to successfully continue the command sequence. the a 0 input can be actively driven by a cmos input signal or tied to v cc or v ss . the remaining three bits in the id byte must be set to 110. figure 2. address/identification byte format instruction byte the next byte sent to the x9420 contains the instruction and register pointer information. the four most significant bits are the instruction. the next two bits point to one of four data registers. the format is shown below in figure 3. figure 3. instruction byte format serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn v h v l v w 8 6 c o u n t e r d e c o d e if wcr = 00[h] then v w = v l if wcr = 3f[h] then v w = v h wiper (wcr) 1 00 11 0a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 0 0 register select instructions x9420
5 fn8195.0 march 7, 2005 the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruct ion is issued. the last two bits are defined as 0. two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: ? xfr data register to wiper counter register ? this instruction transfers the contents of one speci- fied data register to the wiper counter register. ? xfr wiper counter regi ster to data register ?this instruction transfers the contents of the wiper counter register to the specified associated data register. the basic sequence of the two byte instructions is illustrated in figure 4. t hese two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wi per position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its associated registers. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9420; ei ther between the host and one of the data registers or directly between the host and the wcr. these instructions are: ? read wiper counter register ?read the current wiper position of the pot, ? write wiper counter register ?change current wiper position of the pot, ? read data register ?read the contents of the selected data register; ? write data register ?write a new value to the selected data register. ? read status ?this command returns the contents of the wip bit which indica tes if the internal write cycle is in progress. the sequence of these opera tions is shown in figure 5 and figure 6. the final command is increment/decrement. it is different from the other commands, because it?s length is indeterminate. once t he command is issued, the master can clock the wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host . for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 7 and figure 8. figure 4. two-byte instruction sequence 0101110a0 i3 i2 i1 i0 r1 r0 0 0 sck si cs x9420
6 fn8195.0 march 7, 2005 figure 5. three-byte instruction sequence (write) figure 6. three-byte instruction sequence (read) figure 7. increment/decrement instruction sequence figure 8. increment/decrement timing limits 0 101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 11 0 101 0a0 i3 i2 i1 i0 r1 r0 0 0 scl si cs 11 s0 0 0 d5 d4 d3 d2 d1 d0 don?t care 0101110a0 i3 i2 i1 i0 0 0 0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs sck si v w inc/dec cmd issued t wrid voltage out x9420
7 fn8195.0 march 7, 2005 table 3. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 read wiper counter register 1 0 0 1 0 0 0 0 read the contents of the wiper counter register write wiper counter register 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 0 1 1 r 1 r 0 0 0 read the contents of the data register pointed to by r 1 - r 0 write data register 1 1 0 0 r 1 r 0 0 0 write new value to the data register pointed to by r 1 - r 0 xfr data register to wiper counter register 1101r 1 r 0 0 0 transfer the contents of the data register pointed to by r 1 - r 0 to the wiper counter register xfr wiper counter register to data register 1110r 1 r 0 0 0 transfer the contents of the wiper counter register to the data register pointed to by r 1 - r 0 increment/decrement wiper counter register 0 0 1 0 0 0 0 0 enable increment/decrement of the wiper counter register read status (wip bit) 0 1 0 1 0 0 0 1 read the status of the internal write cycle, by check- ing the wip bit. x9420
8 fn8195.0 march 7, 2005 instruction format notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the wiper counter register ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) read the contents of the register pointed to by r1 - r0. write data register (dr) write a new value to the register pointed to by r1 - r0. transfer data register (dr) to wiper counter register (wcr) transfer the contents of the register pointed to by r1 - r0 to the wcr. cs falling edge device type identifier device addresses instruction opcode wiper position (sent by x9420 on so) cs rising edge 0101110 a 0 1001000000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode data byte (sent by host on si) cs rising edge 0101110 a 0 1010000000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by x9420 on so) cs rising edge 0101110 a 0 1011 r 1 r 0 0000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0101110 a 0 1100 r 1 r 0 0000 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge 0101110 a 0 1101 r 1 r 0 00 x9420
9 fn8195.0 march 7, 2005 transfer wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) read status cs falling edge device type identifier device addresses instruction opcode register addresses cs rising edge high-voltage write cycle 0101110 a 0 1110 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode increment/decrement (sent by master on sda) cs rising edge 0101110 a 0 00100000i/di/d. . . .i/di/d cs falling edge device type identifier device addresses instruction opcode data byte (sent by x9420 on so) cs rising edge 0101110 a 0 010100010000000 w i p x9420
10 fn8195.0 march 7, 2005 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on sck, scl or any address input with respect to v ss ........... -1v to +7v voltage on v+ (referenced to v ss )........................ 10v voltage on v- (referenced to v ss )........................-10v (v+) - (v-) .............................................................. 12v any v h /r h , v l /r l , v w /r w ........................... v- to v+ lead temperature (soldering, 10 seconds)........ 300c i w (10 seconds)..................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sect ions of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended operating condi tions unless otherwise stated.) notes: (1) absolute linearity is utilized to dete rmine actual wiper voltage versus expected voltage as det ermined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. it is a measure of the error in step size. (3) mi = rtot/63 or (v h - v l )/63, single pot. (4) typical = individual array resolution. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 20 % power rating 50 mw 25c, each pot i w wiper current 3 ma r w wiper resistance 150 250 ? wiper current = 1ma, v+/v- = 3v 40 100 ? wiper current = 1ma, v+/v- = 5v vv+ voltage on v+ pin x9420 +4.5 +5.5 v x9420-2.7 +2.7 +5.5 vv- voltage on v- pin x9420 -5.5 -4.5 v x9420-2.7 -5.5 -2.7 v term voltage on any v h /r h , v l /r l , v w /r w v- v+ v noise -140 dbv ref: 1khz resolution (4) 1.6 % see note 5 absolute linearity (1) 1 mi (3) v w(n)(actual) - v w(n)(expected) relative linearity (2) 0.2 mi (3) v w(n + 1) - [v w(n) + mi ] temperature coefficient of r total 300 ppm/c see note 5 ratiometric temperature coefficient 20 ppm/c see note 5 c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3 i al rh, ri, rw leakage current 0.1 10 a vin = v- to v+. device is in stand-by mode. recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) limits x9420 5v 10% x9420-2.7 2.7v to 5.5v x9420
11 fn8195.0 march 7, 2005 d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) endurance and data retention capacitance power-up timing power-up requirements (power-up sequencing can affect correct recall of the wiper registers) the preferred power-on sequenc e is as follows: first v cc , then v+ and v-, and then the potentiometer pins, r h , r l , and r w . voltage should not be applied to the potentiomet er pins before v+ or v- is applied. the v cc ramp rate specification should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. if v cc powers down, it should be held below 0.1v for more than 1 second before powering up again in order for proper wiper register recall. also, v cc should not reverse polarit y by more than 0.5v. recall of wiper position will not be complete until v cc , v+ and v- reach their final value. notes: (5) this parameter is periodically sampled and not 100% tested. (6) t pur and t puw are the delays required from the ti me the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 a f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (non-volatile write) 1maf sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 a sck = si = v ss , addr. = v ss i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage -0.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c out (5) output capacitance (so) 8 pf v out = 0v c in (5) input capacitance (a0, si, and sck) 6 pf v in = 0v symbol parameter max. max. units t pur (6) power-up to initiation of read operation 1 1 ms t puw (6) power-up to initiation of write operation 5 5 ms t r v cc v cc power-up ramp 0.2 50 v/msec x9420
12 fn8195.0 march 7, 2005 a.c. test conditions equi valent a.c. load circuit ac timing i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 ? 100pf sda output symbol parameter min. max. units f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns x9420
13 fn8195.0 march 7, 2005 high-voltage wr ite cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 450 ns waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9420
14 fn8195.0 march 7, 2005 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo x9420
15 fn8195.0 march 7, 2005 xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck si msb lsb v w t wrl ... so high impedance ... cs sck so si addr t wrid high impedance v w ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction) x9420
16 fn8195.0 march 7, 2005 applications information electronic potentiometers provide thre e powerful application advan tages: (1) the variability and reliability of a solid- state potentiometer, (2) the flexibility of computer-based digital controls, and (3 ) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. basic configurations of electronic potentiometers basic circuits v r v w v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current v h v l noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /cr 1 +r 2 } v o (max) v ll = {r 1 /cr 1 +r 2 } v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } } +5v -5v lm308a cascading techniques buffered reference voltage ? + +5v r 1 +v -5v v w v w v out = v w op-07 v w v w +v +v +v x (a) (b) x9420
17 fn8195.0 march 7, 2005 packaging information 0.320 (8.13) 0.290 (7.37) typ. 0.311 (7.90) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 0.700 (17.78) ref. 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.070 (1.78) 0.015 (0.38) pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.038 (0.97) typ. 0.060 (1.52) 0.310 (7.87) 0.220 (5.59) 0.098 (2.49) ?? 0 15 16-lead hermetic dual in-line package type d note: all dimensions in inches (in pare ntheses in millimeters) 0.735 (18.67) seating plane 0.005 (0.13) min. 0.015 (0.38) 0.008 (0.20) 0.200 (5.08) ?? 0.150 (3.81) min. 0.775 (19.69) x9420
18 fn8195.0 march 7, 2005 packaging information 16-lead plastic soic (300 mil body) package type s note: all dimensions in inches (in parentheses in millimeters) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.403 (10.2 ) 0.413 ( 10.5) (4x) 7 0.420" 0.050" typical 0.030" typical 16 places footprint 0.010 (0.25) 0.020 (0.50) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 0.050" typical 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) 0.015 (0.40) 0.050 (1.27) x9420
19 fn8195.0 march 7, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x9420
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8195.0 march 7, 2005 ordering information device v cc limits blank = 5v 10% -2.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = -40 c to +85 c m = military = ?55 c to +125 c package p = 16-lead plastic dip s = 16-lead soic v = 14-lead tssop potentiometer organization w = 10k y = 2.5k x9420 p t v y x9420

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